Given today's high clock rates and transmission line effects when signals must travel between integrated circuit chips, skew between different data bits in the same bus becomes a problem. As a system heats and cools during operation, and/or develops hot and cool spots, the skew between data bits can likewise change as data bit signals and strobe signals travel off chip and between chips through various system-level paths. Also, as these phenomenon dynamically change during operation, the skew between data bits can likewise change. Therefore, it would be useful to have a way to perform bit leveling from time to time during system operation, and to do so quickly, and to perform bit leveling independently for each data bit on a data bus.
One application where a dynamic bit leveling capability is especially useful for compensating for variable system-level delays is that of dynamic memory interfaces where DQ data bits can develop a skew problem with respect to the DQS strobe used to sample them. Jitter can also develop between data bits and strobes, and it would also be useful to resolve jitter issues while performing a bit-leveling function.